台积电确认正在开发 1.4 纳米和 1.0 纳米芯片制造技术。该公司在其新的路线图上显示，这些制程将分别被称为 A14 和 A10。至于台积电首批 1.4 纳米和 1.0 纳米芯片何时问世，目前还不清楚。在其逻辑技术未来展望的幻灯片中，台积电表示 A14 处于 “开发中”，而 N2 工艺仍计划于 2025 年推出。由于 N2P（N2 工艺的改进版本）预计将在 2026 年面市，因此看起来台积电首批采用 1.4 纳米制程生产的芯片最早可能要到 2027 年才会问世。据 Tom’s Hardware 网站报道，在 A14 工艺中很可能会采用第二代或第三代全环绕场效应晶体管（GAA-FET），而非垂直堆叠互补场效应晶体管（CFET）。在演示文稿的另一张幻灯片中展望到 2030 年，首次提及了 A10 工艺。因此，台积电似乎计划在七年后开始生产 1.0 纳米芯片，尽管目前还无法确定是否能如期实现。
TSMC has confirmed that it is developing 1.4-nanometer and 1.0-nanometer chip manufacturing technologies. The company’s new roadmap shows that these processes will be called A14 and A10, respectively. It is currently unclear when TSMC’s first batch of 1.4-nanometer and 1.0-nanometer chips will be available. In its slide on the future prospects of logic technology, TSMC states that the A14 is “under development,” while the N2 process is still planned for launch in 2025. Since the improved version of N2P (N2 process) is expected to hit the market in 2026, it appears that TSMC’s first batch of chips produced using the 1.4-nanometer process may not debut until as early as 2027.
It is currently unclear how TSMC’s 1.4-nanometer process will be implemented. According to a report from Tom’s Hardware website, the A14 process may likely adopt second or third-generation Gate-All-Around Field-Effect Transistors (GAA-FET), rather than vertically stacked Complementary Field-Effect Transistors (CFET). In another slide in the presentation looking ahead to 2030, mention of the A10 process was made for the first time. Therefore, it seems that TSMC plans to start producing 1.0-nanometer chips seven years later, although it remains uncertain whether this can be achieved as scheduled.
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